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authorhachem <im@hachem.wtf>2024-10-18 09:34:36 +0200
committerhachem <im@hachem.wtf>2024-10-18 09:34:36 +0200
commit5f058c9b67e0f96e0dd89bbeff0afe8e08bde25b (patch)
tree7546702edc4d6e2c66c1440753c31387b38dea9f /libpsi-core/src/core/classical_components.rs
parent7cc3c78a24b51a58d44e1baff20b86292662390e (diff)
Allow named registers and tiny refactor
Diffstat (limited to 'libpsi-core/src/core/classical_components.rs')
-rw-r--r--libpsi-core/src/core/classical_components.rs63
1 files changed, 63 insertions, 0 deletions
diff --git a/libpsi-core/src/core/classical_components.rs b/libpsi-core/src/core/classical_components.rs
new file mode 100644
index 0000000..6710e9d
--- /dev/null
+++ b/libpsi-core/src/core/classical_components.rs
@@ -0,0 +1,63 @@
+use core::ops;
+
+#[derive(Clone, Copy)]
+pub struct ClassicalBit<'a> {
+ state: bool,
+ name: &'a str,
+}
+
+#[derive(Clone)]
+pub struct ClassicalRegister<'a> {
+ bits: Vec<ClassicalBit<'a>>,
+ name: &'a str,
+}
+
+impl<'a> ClassicalBit<'a> {
+ pub fn new(name: &'a str, state: bool) -> ClassicalBit {
+ ClassicalBit { name, state }
+ }
+
+ pub fn get_name(&self) -> &'a str {
+ self.name
+ }
+
+ pub fn get_state(&self) -> bool {
+ self.state
+ }
+}
+
+impl<'a> ClassicalRegister<'a> {
+ pub fn new(name: &'a str, names: &'a [&'a str]) -> ClassicalRegister<'a> {
+ let mut bits: Vec<ClassicalBit<'a>> = Vec::new();
+ for i in 0..names.len() {
+ bits.push(ClassicalBit::new(names[i], false));
+ }
+ ClassicalRegister { name, bits }
+ }
+
+ pub fn set_bits(&mut self, bits: Vec<ClassicalBit<'a>>) {
+ self.bits = bits;
+ }
+
+ pub fn get_bits(&self) -> Vec<ClassicalBit<'a>> {
+ self.bits.clone()
+ }
+
+ pub fn get_name(&self) -> &'a str {
+ self.name
+ }
+}
+
+impl<'a> ops::Index<usize> for ClassicalRegister<'a> {
+ type Output = ClassicalBit<'a>;
+
+ fn index(&self, index: usize) -> &Self::Output {
+ &self.bits[index]
+ }
+}
+
+impl<'a> ops::IndexMut<usize> for ClassicalRegister<'a> {
+ fn index_mut(&mut self, index: usize) -> &mut Self::Output {
+ &mut self.bits[index]
+ }
+}